The existence of structural, control, and data hazards presents a major challenge in designing an advanced pipeline/superscalar\r\nmicroprocessor. An efficient memory hierarchy cache-RAM-Disk design greatly enhances the microprocessor�s performance.\r\nHowever, there are complex relationships among the memory hierarchy and the functional units in the microprocessor. Most\r\npast architectural design simulations focus on the instruction hazard detection/prevention scheme from the viewpoint of function\r\nunits. This paper emphasizes that additional inboard memory can be well utilized to handle the hazardous conditions. When the\r\ninstruction meets hazardous issues, the memory latency can be utilized to prevent performance degradation due to the hazard\r\nprevention mechanism. By using the proposed technique, a better architectural design can be rapidly validated by an FPGA at the\r\nstart of the design stage. In this paper, the simulation results prove that our proposed methodology has a better performance and\r\nless power consumption compared to the conventional hazard prevention technique.
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